In computing, a data bus is simply a device which facilitates the transfer of data between data processing elements. In telecommunications applications, data busses can transfer data between separate elements on a board or even between specific instantiations of logic on a single chip, like an FPGA or an ASIC. A common data bus in these applications is the interface between serializing/deserializing (SERDES) devices and a data framer. In the interests of interoperability, the interface is typically instantiated in accord with the SERDES Framer Interface (SFI) implementation agreements published by the Optical Internetworking Forum (OIF). The latest of these agreements, rather than addressing a particular rate of data transfer, is directed towards the needs of future networks which will operate at rates beyond 40G. The 40G SFI standard, SFI-5, features four data transmission lanes as well as a fifth lane for the transmission of deskew data for the data frames being transmitted across the bus. Based on this architecture, the latest OIF standard details the implementation of an SFI bus that can incorporate 4-20 data lanes with a single deskew lane, and theorizes the implementation of even larger bus sizes beyond 20 lanes for future applications at speeds which remain in the realm of theory.
This latest scalable bus implementation is known as SFI-S. The OIF's SFI-S implementation is an expansion upon the concepts of the SFI-5 and SFI-4 standards. At its smallest size (4+1 lanes), SFI-5 closely resembles SFI-5, although some differences exist in SFI-S's deskew lane. The core concept of the OIF's SFI standards is a single 10 Gb/s data transmission lane with an accompanying deskew lane (SFI-4). Successive iterations of the standard offer increasingly larger numbers of data lanes transmitting multiplexed data frames. As these architectures have become more complex and consequently faster, the issue of skew has become more important: higher data rates mean greater sensitivity to timing errors.
As indicated above, the SFI standards address the issue of skew by including a deskew, or reference, lane in the design of the data bus. The deskew lane transmits a reference frame which allows deskew elements in the SERDES or framer to measure skew in the incoming data, and adjust the transmission of the data accordingly. The transmitted reference lane consists of a number of five-bit elements which are themselves comprised of four samples taken from the data lanes followed by a parity of those four bits. The parity bits may be even or odd, dependent upon their position in the reference frame. The SFI-S implementation agreement states that every reference frame must begin with an even parity element and end with an odd parity element. Any additional elements required alternate even and odd parity, but always begin with an even parity element. Thus, a four-element frame is defined as even, even, odd, odd. The number of required elements is dependent upon the number of data lanes; the maximum number of data lanes supported by a reference lane is n×4,where n is the number of elements, bearing in mind that there must be at least 2 elements per frame. Thus, 4-8 data lanes require a 2-element reference frame, 9-12 lanes require a 3-element reference frame, 13-16 lanes require a 4-element reference frame, and 17-20 lanes require a 5-element reference frame. As noted above, each of these elements are composed of four bit samples from the data lanes. The sampling method is defined in the implementation agreement:                The bit samples of the reference frame shall be filled, starting at the highest number data lane RX/TXDATA(n−1), which is filed into the first sample position of the even parity element at the beginning of the frame. RX/TXDATA(n−2) is filled into the second sample position and so on, until RX/TXDATA(0) is filled in. If the RX/TXDATA(0) sample does not land in the last sample position of the frame ending odd element, the remaining bit samples are filled again, starting from RX/TXDATA(n−1). (SFI-S)        
This sampling method, for a ten-lane configuration, is illustrated in FIG. 1. The deskew operation is dependent upon the proper construction of reference frames; it is therefore essential that the reference frames begin with the correct bits, so that the lanes of the data bus may be correctly deskewed. It is possible, however, that sampling may begin with the incorrect bit, due to a timing error or skew. If such an event occurs, it is necessary to spend additional on-board resources to hunt for the correct starting bit of the reference frames. A common means of rectifying this issue is to employ a bit-shifting element to alter the starting position of bit sampling for the reference lane. Employing such a bit-shifting element requires the use of additional resources, even if an already-present shifting element must be reconfigured to alter the position of the sampled bits. Thus it is necessary to employ a method which can address the issue of a misaligned reference lane without further requiring the use of additional on-board resources.